With the recent increase of integration density of a DRAM, a cell size and an area to be occupied by a capacitor of the DRAM cell tend to reduce, respectively. In order to keep a capacitance of such capacitor at an acceptable value, a stacked capacitor or a trench stacked capacitor has been used since it can provide a large capacitor area therein and it is capable of reducing interference between DRAM cells, and a variety of variation has been made to this basic stacked capacitor so as to increase the surface area. The widely adopted stacked capacitor includes for example cylindrical and fin type capacitor.
Generally, the stacked capacitor may be classified into COB(capacitor over bit line) structure and CUB(capacitor under bit line) structure from the fabrication sequence standpoint. The significant difference between them is the time when the capacitor is formed, i.e., after forming the bit line(COB) or before forming the bit line(CUB).
However, the conventional process for a DRAM capacitor with COB structure has some drawbacks in very high density devices such as Giga bit scale DRAM with 0.30 pitch application. For example, a sub-quarter micron resist pattern and high aspect ratio contact hole etching is significant obstacle to conventional photolithography technique and thereby deteriorating photo pattern and uniformity and reducing misalignment margin between storage node contact hole and storage node, and in severe case the short between the bit line and storage node contact hole may arise.